HBM Competition Heats Up! SK Hynix Explores New Packaging Solutions to Meet Nvidia's Peak Performance Goals

According to South Korea’s ZDNet, SK Hynix is advancing next-generation packaging technology to improve the stability and performance of HBM4. Currently, this technology is in the verification stage.

Because the I/O (input/output signals) of HBM4 has doubled to 2,048, there is an increased risk of signal interference. While this expansion boosts bandwidth, it also presents challenges related to voltage and other factors. To enhance stability, SK Hynix plans to increase the thickness of some upper-layer DRAM chips and reduce the spacing between DRAM layers, preventing overall package height from increasing, while also lowering power consumption for the top-layer power supply and improving power efficiency.

Traditionally, DRAM chips are thinned by grinding the back surface to meet the 775-micron thickness requirement of HBM4. However, excessive thinning can reduce performance and increase sensitivity to external shocks, prompting SK Hynix to consider increasing chip thickness.

However, narrower gaps make it more difficult to inject mold bottom fill material (MUF) into the gaps. To protect and insulate, the packaging process requires uniform MUF filling to prevent chip defects. Therefore, SK Hynix has developed a new packaging technology aimed at narrowing DRAM spacing while maintaining stable yield without significantly altering existing processes or equipment.

Recent internal tests have shown positive results. If commercialized, this technology is expected not only to meet NVIDIA’s peak performance requirements for HBM4 but also to significantly enhance the performance of next-generation products.

Earlier reports indicated that NVIDIA might lower its initial performance requirements for HBM4 to around 10 Gbps. Semiconductor analysis firm Semianalysis stated that NVIDIA initially set a total bandwidth target of 22 TB/s for the Rubin chip, but memory suppliers seem unable to meet this demand. It is expected that initial shipments will be below this, close to 20 TB/s (equivalent to 10 Gbps per HBM4 pin).

In this context, to pursue higher market share, major memory manufacturers have already begun a performance race for HBM. For example, Samsung has been implementing numerous measures, including increasing DRAM chip size and introducing a new power delivery architecture (PDN segmentation technology) to reduce HBM defect rates, based on more advanced 1c DRAM technology.

According to the latest report from TrendForce, as AI infrastructure expands, demand for GPUs is also growing. It is expected that after NVIDIA’s Rubin platform mass production begins, it will drive demand for HBM4. Currently, the verification programs for HBM4 at the three major memory manufacturers are nearing completion, expected to finish sequentially in the second quarter of 2026.

From the progress of various manufacturers, Samsung is expected to lead the verification process due to its superior product stability and will begin mass production in the second quarter after passing verification. SK Hynix continues to push forward and is likely to leverage its existing collaboration with NVIDIA on HBM to maintain an advantage in supply allocation. Micron’s verification process is relatively slower but is also expected to complete in the second quarter.

(Source: Cailian Press)